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1. general description the PCF8534 is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 60 segments and can easily be cascaded for larger lcd applications. the PCF8534 is compatible with most microprocessors / microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized using a display ram with auto-incremented addressing, hardware subaddressing and display memory switching (static and duplex drive modes). 2. features PCF8534 universal lcd driver for low multiplex rates rev. 00.05 ? 20 february 2007 preliminary datasheet ? single-chip lcd controller / driver ? selectable backplane drive configuration: static or 2 / 3 / 4 backplane multiplexing ? selectable display bias configuration: static, 1 ? 2 or 1 ? 3 ? internal lcd bias generation with voltage-follower buffers ? 60 segment drives: up to thirty 8-segment numeric characters; up to sixteen 15-segment alphanumeric characters; or any graphics of up to 240 elements ? 60 x 4-bit ram for display data storage ? auto-incremented display data loading across device subaddress boundaries ? display memory bank switching in static and duplex drive modes ? versatile blinking modes ? lcd and logic supplies may be separated ? wide power supply range: from 1.8to5.5v ? wide lcd supply range: from 2.5 v for low threshold lcds and up to 6.5 v for guest-host lcds and high threshold (automobile) twisted nematic lcds ? low power consumption ? 400 khz i 2 c-bus interface ? ttl/cmos compatible ? compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers ? may be cascaded for 2 lcd applications ? no external components ? manufactured in silicon gate cmos process.
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 2 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 3. ordering information table 1. ordering information type number topside mark package name description version PCF8534h PCF8534h lqfp80 plastic, low profile, quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 3 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 4. block diagram fig 1. PCF8534 block diagram -',v i 2 c-bus control 0#& 6 ,#$ 6 33 #,+ 39.# /3# 3#, 3$! &orfn6hohfw dqg7lplqj %olqnhu wlphedvh /&'9rowdjh 6hohfwru /&'%ldv *hqhudwru 'lvsod\ &rqwuro 2xwsxw%dqn6hohfw dqg%olqn&rqwuro 'lvsod\5hjlvwhu 'lvsod\6hjphqw2xwsxwv 6wr6 %3 %3 %3 %3 'lvsod\5$0 %dfnsodqh 2xwsxwv 2vfloodwru 3rzhurq 5hvhw , &%xv &rqwuroohu &rppdqg 'hfrgh :ulwh'dwd &rqwuro 'dwd3rlqwhudqg $xwr,qfuhphqw 6xe$gguhvv &rxqwhu 6$ 6 $$ $ $ $ ,qsxw )lowhuv
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 4 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 5. pinning information 5.1 pinning fig 2. PCF8534 pin configuration PCF8534 mdb073v02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s 31 s 33 s 34 s 35 s 36 s 37 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 s3 0 s2 9 s2 8 s2 7 s2 6 s2 5 s2 4 s2 3 s2 2 s2 1 s2 0 s1 9 s1 8 s1 7 s1 6 s1 5 17 18 19 20 s 32 s 40 s 39 s 38 s 41 s 42 s 43 s 44 s 45 s 46 s 47 s 48 s 49 s 50 64 63 62 61 s1 4 s1 3 s1 2 s1 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 s51 s53 s54 s55 s56 s57 s52 bp0 s59 s58 bp1 bp2 bp3 n.c. n.c. n.c. n.c. sda scl clk s10 s8 s7 s6 s5 s4 s9 s1 s2 s3 s0 vlc d vss sa0 a2 a1 a0 osc syn c vdd table 2. pin allocation table pin symbol pin symbol 1 s31 41 v dd 2 s32 42 sync 3 s33 43 osc 4 s34 44 a0 5 s35 45 a1 6 s36 46 a2 7 s37 47 sa0 8 s38 48 v ss 9 s39 49 v lcd
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 5 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 5.2 pin description 10 s40 50 s0 11 s41 51 s1 12 s42 52 s2 13 s43 53 s3 14 s44 54 s4 15 s45 55 s5 16 s46 56 s6 17 s47 57 s7 18 s48 58 s8 19 s49 59 s9 20 s50 60 s10 21 s51 61 s11 22 s52 62 s12 23 s53 63 s13 24 s54 64 s14 25 s55 65 s15 26 s56 66 s16 27 s57 67 s17 28 s58 68 s18 29 s59 69 s19 30 bp0 70 s20 31 bp1 71 s21 32 bp2 72 s22 33 bp3 73 s23 34 n.c. 74 s24 35 n.c. 75 s25 36 n.c. 76 s26 37 n.c. 77 s27 38 sda 78 s28 39 scl 79 s29 40 clk 80 s30 table 2. pin allocation table ?continued pin symbol pin symbol table 3. pin description symbol pin description sda 38 i 2 c-bus serial data input / output scl 39 i 2 c-bus serial clock input clk 40 external clock input / output v dd 41 supply voltage sync 42 cascade synchronization input / output
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 6 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6. functional description the PCF8534 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 60 segments. the display configurations possible with the PCF8534 depend on the number of active backplane outputs required; a selection of display configurations is given in table 4 . all of the display configurations given in ta b le 4 can be implemented in the typical system shown in figure 3 . the host microprocessor / microcontroller maintains the 2-line i 2 c-bus communication channel with the PCF8534. the internal oscillator is selected by connecting pad osc to v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are the power supplies (v dd , v ss and v lcd ) and the lcd panel selected for the application. osc 43 internal oscillator enable input a0, a1 and a2 44 to 46 subaddress inputs sa0 47 i 2 c-bus slave address input: [0] v ss 48 logic ground v lcd 49 lcd supply voltage bp0, bp1, bp2 and bp3 30 to 33 lcd backplane outputs s0 to s59 50 to 80 and 1 to 29 lcd segment outputs table 3. pin description symbol pin description table 4. selection of display configurations number of 7 segment numeric 14 segment numeric dot matrix backplanes segments digits indicator symbols characters indicator symbols 4 240 30 30 16 16 240 (4 x 60) 3 180 22 26 12 12 180 (3 x 60) 2 120 15 15 8 8 120 (2 x 60) 16071144 60 (1 x 60)
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 7 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.1 power-on-reset at power on the PCF8534 resets to a starting condition as follows: 1. all backplane outputs are set to v lcd . 2. all segment outputs are set to v lcd . 3. the drive mode ?1 : 4 multiplex with 1 ? 3 bias? is selected. 4. blinking is switched off. 5. input and output bank selectors are reset (as defined in table 7 old datasheet). 6. the i 2 c-bus interface is initialized. 7. the data pointer and the subaddress counter are cleared. 8. display disabled. you must avoid data transfers on the i 2 c-bus for 1 ms following power on to allow the reset action to complete. 6.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider of the three series resistors connected between v lcd and v ss . the centre resistor can be switched out of the circuit to provide a 1 ? 2 bias voltage level for the 1:2 multiplex configuration. 6.3 lcd voltage selector the lcd voltage selector co-ordinates the multiplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by mode set commands from the command decoder. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v op and the resulting discrimination ratios (d), are shown in table 5 . fig 3. typical system configuration host micro- processor/ micro- controller r t r 2c b sda scl osc 60 segment drives 4 backplanes lcd panel (up to 240 elements) PCF8534 a0 a1 a2 sa0 v dd v ss v ss v dd v lcd mgl744v0 2
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 8 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates a practical value for v op is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. in the static drive mode a suitable choice is v op > 3v th . multiplex drive ratios of 1:3 and 1:4 with 1 ? 2 bias are possible but the discrimination and hence the contrast ratios are smaller e.g.: the advantage of these modes is a reduction of the lcd full-scale voltage v op as follows: ? 1:3 multiplex ( 1 ? 2 bias): ? 1:4 multiplex ( 1 ? 2 bias): these compare with v op =3 x v off(rms) when 1 ? 3 bias is used. note: v op =v lcd . 3 1.732 for 1:3 multiplex or 21 3 --------- - 1.528 = ?? ?? for 1:4 multiple x = v op 6v off rms () 2.449v off rms () == v op 43 () 3 -------------------- - 2.309v off rms () == table 5. preferred lcd drive modes: summary of characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 2 3 1 ? 2 0.354 0.791 2.236 1:2 2 4 1 ? 3 0.333 0.745 2.236 1:3 3 4 1 ? 3 0.333 0.638 1.915 1:4 4 4 1 ? 3 0.333 0.577 1.732 v off ms () v op - --------------------- - v on ms () v op - --------------- --- - d v on ms () v off ms () ------------------- --- - =
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 9 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.4 lcd drive m ode waveforms 6.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 4 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 4. static drive mode waveforms mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd s tate 1 0 v bp0 s n s n + 1 s tate 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off ) t frame
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 10 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the PCF8534 allows the use of 1 ? 2 bias or 1 ? 3 bias in this mode as shown in figure 5 and figure 6 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791 v lcd . v state2 (t) = v (sn) (t) ? v bp1 (t). v off(rms) = 0.354 v lcd . fig 5. waveforms for the 1:2 multiplex drive mode with 1 ? 2 bias. mgl746 s tate 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 s tate 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 ? v lcd ? v lcd ? v lcd /2 ? v lcd /2 s n s n + 1 t frame
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 11 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745 v lcd . v state2 (t) = v (sn) (t) ? v bp1 (t). v off(rms) = 0.333 v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 ? 3 bias. mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segment s state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 s n s n + 1 t frame v ss v lcd 2v lcd /3 v lcd /3
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 12 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 7 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638 v lcd . v state2 (t) = v (sn) (t) ? v bp1 (t). v off(rms) = 0.333 v lcd . fig 7. waveforms for the 1:3 multiplex drive mode. mgl748 s tate 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 s tate 2 (a) waveforms at driver. bp2 s n s n + 1 s n + 2 t frame v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 13 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577 v lcd . v state2 (t) = v (sn) (t) ? v bp1 (t). v off(rms) = 0.333 v lcd . fig 8. waveforms for the 1:4 multiplex drive mode. mgl749 s tate 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 s tate 2 bp2 (a) waveforms at driver. bp3 s n s n + 1 s n + 2 s n + 3 t frame v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 14 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.5 oscillator 6.5.1 internal clock the internal logic and the lcd drive signals of the PCF8534 are timed either by the built-in oscillator or from an external clock. when the internal oscillator is used, you must connect pad osc to v ss . in this event, the output from pad clk provides the clock signal for cascaded PCF8534?s in the system. after power-up, sda must be high to guarantee that the clock starts. 6.5.2 external clock the condition for external clock is made by tying pad osc to v dd ; pad clk then becomes the external clock input. the clock frequency (f clk ) determines the lcd frame frequency. a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state. 6.6 timing the timing of the PCF8534 organizes the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications the synchronization signal (sync ) maintains the correct timing relationship between the PCF8534?s in the system. the timing also generates the lcd frame frequency which it derives as an integer division of the clock frequency (see table 6 ). the frame frequency is a fixed division of the internal clock or of the frequency applied to pad clk when an external clock is used. 6.7 display register the display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch, the lcd segment outputs and one column of the display ram. 6.8 segment outputs the lcd drive section includes 60 segment outputs (s0 to s59) which must be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. when less than 60 segment outputs are required the unused segment outputs must be left open-circuit. 6.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1:2 multiplex drive mode bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 15 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.10 display ram the display ram is a static 60 x 4-bit ram which stores lcd data. a logic 1 in the ram bit map indicates the on-state of the corresponding lcd segment; similarly, a logic 0 indicates the off-state. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the first ram column corresponds to the 60 segments operated with respect to backplane bp0 (see figure 9 ). in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with bp1, bp2 and bp3 respectively. when display data is transmitted to the PCF8534 the display bytes received are stored in the display ram in accordance with the selected lcd drive mode. the data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. depending on the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1:2 mux mode the ram data is stored every second bit. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 10 ; the ram filling organization depicted applies equally to other lcd types. with reference to figure 10 , in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display ram addresses. in the 1:2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display ram addresses. in the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. in the 1:4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display ram addresses. table 6. lcd frame frequencies frame frequency nominal frame frequency (hz) 64 f clk 24 ---------- - fig 9. display ram bit map showing direct relationship between backplane outputs, display ram addresses and segment outputs, and between bits in a ram word and backplane outputs. u llpagewidth display2!-addressesrows segmentoutputs3 display2!-bits columns backplaneoutputs "0 -',v
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 16 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load data pointer command. following this, an arriving data byte is stored starting at the display ram address indicated by the data pointer thereby observing the filling order shown in figure 10 . the data pointer is automatically incremented in accordance with the chosen lcd configuration. that is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1:2 multiplex drive mode), by three (1:3 multiplex drive mode) or by two (1:4 multiplex drive mode). if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer must be re-written prior to further ram accesses. 6.12 subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device select command. if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to extremely efficient data loading in cascaded applications. when a series of display bytes are sent to the display ram, automatic wrap-over to the next PCF8534 occurs when the last ram address is exceeded. subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1 : 3 multiplex mode). the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 6.13 output bank selector the output bank selector selects one of the four bits per display ram address for transfer to the display latch. the actual bit selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. in 1:4 multiplex, all ram addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. similarly in 1:3 multiplex, bits 0, 1 and 2 are selected sequentially. in 1:2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. the sync signal will reset these sequences to the following starting points; bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. the PCF8534 includes a ram bank switching feature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. in the 1:2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 17 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 6.14 input ba nk selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1:2 drive mode by using the bank select command. the input bank selector functions independently to the output bank selector. 6.15 blinker the display blinking capabilities of the PCF8534 are very versatile. the whole display can be blinked at frequencies selected by the blink command. the blinking frequencies are integer multiples of the clock frequency. the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see ta b l e 7 . an additional feature is for an arbitrary selection of lcd segments to be blinked. this applies to the static and 1:2 lcd drive modes and is implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be specified by the blink command. in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at fixed time intervals. if the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode set command. table 7. blinking frequencies blinking mode normal operating mode ratio normal blinking frequency off - blinking off 2 hz 2 hz 1 hz 1 hz 0.5 hz 0.5 hz f clk 768 ---------- - f clk 1536 ----------- - f clk 3072 ----------- -
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 18 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates x = data bit unchanged fig 10. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c bus. mgl75 1 s n + 2 s n + 1 s n + 7 s n s n s n + 3 s n + 5 s n + 2 s n + 3 s n + 1 s n + 1 s n + 1 s n + 2 s n s n + 6 s n s n + 4 dp dp dp dp a f b g e c d a f b g e c d a f b g e c d a f b g e c d bp0 bp0 bp0 bp1 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n1 n2 n3 n4 n5 n6 n7 bit/ bp n a b x x 0 1 2 3 f g x x e c x x d dp x x n1 n2 n3 bit/ bp n b dp c x 0 1 2 3 a d g x f e x x n1 n2 bit/ bp n a c b dp 0 1 2 3 f e g d n1 bit/ bp cbaf geddp abf gecddp bdpcadgf e ac bdpf e g d msb lsb msb lsb msb lsb msb lsb drive mode static 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 19 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 7. application design-in information 7.1 characteristics of the i 2 c bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer is initiated only when the bus is not busy. 7.2 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. bit transfer is illustrated in figure 11 . 7.3 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are illustrated in figure 12 . 7.4 system configuration a device generating a message is a ?transmitter?, a device receiving a message is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves?. the system configuration is illustrated in figure 13 . fig 11. bit transfer mba607 data line stable; data valid change of data allowed s da s cl fig 12. definition of start and stop conditions mbc622 s da s cl p stop condition sd a sc l s start condition
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 20 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 7.5 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 14 . 7.6 PCF8534 i 2 c-bus controller the PCF8534 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the PCF8534 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferred command data and on the hardware subaddress. fig 13. system configuration mga807 sda s cl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 14. acknowledgement of the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output b y transmitter data output by receiver scl from master
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 21 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates in single device application, the hardware subaddress inputs a0, a1 and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1 and a2 are tied to v ss or v dd in accordance with a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 7.7 input filters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines. 7.8 i 2 c-bus protocol two i 2 c-bus slave addresses (01110000 and 01110010) are reserved for the PCF8534. the least significant bit of the slave address that a PCF8534 will respond to is defined by the level tied at its input sa0. the PCF8534 is a write only device and will not respond to a read access. therefore, two types of PCF8534 can be distinguished on the same i 2 c-bus which allows: 1. up to 16 PCF8534?s on the same i 2 c-bus for very large lcd applications 2. the use of two types of lcd multiplex on the same i 2 c-bus. the i 2 c-bus protocol is shown in figure 15 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two PCF8534 slave addresses available. all PCF8534?s with the corresponding sa0 level acknowledge in parallel to the slave address, but all PCF8534?s with the alternative sa0 level ignore the whole i 2 c-bus transfer. after acknowledgement, a control byte follows which defines if the next byte is ram or command information. the control byte also defines if the next following byte is a control byte or further ram/command data. in this way it is possible to configure the device then fill the display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed PCF8534?s connected to the bus. the display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8534 device. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed PCF8534. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart an i 2 c-bus access.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 22 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates fig 15. i 2 c-bus protocol e xamples a ) transmit two bytes of ram data mgl75 2 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b ) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c ) transmit one command byte and two ram bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a co rs (1) c 0 = 0; last control byte (2) c 0 = 1; control bytes continue (3) rs = 0; data is a command byte (4) rs = 1; data is a display byte fig 16. control byte format mgl753 unused co rs msb lsb
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 23 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 7.9 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the five commands available to the PCF8534 are defined in ta b le 8 . table 8. definition of PCF8534 commands command opcode options description mode set 1100ebm1m0 tab le 9 defines lcd drive mode tab le 1 0 defines lcd bias configuration tab le 11 defines display status; the possibility to disable the display allows implementation of blinking under external control load data pointer 0 p6 p5 p4 p3 p2 p1 p0 tab le 1 2 7 bits of immediate data, bits p6 to p0, are transferred to the data pointer to define one of 8 hardware subaddresses device select 11100a2a1a0 tab le 1 3 3 bits of immediate data, bits a0 to a3 are transferred to the subaddress counter to define one of 8 hardware subaddresses bank select 1 1 1 1 1 0 i o tab le 1 4 defines input bank selection (storage of arriving display data) tab le 1 5 defines output bank selection (retrieval of lcd display data); the bank select command has no effect in 1:3 or 1:4 multiplex drive modes blink 1 1 1 1 0 a bf bf tab le 1 6 defines the blinking frequency 10 tab le 1 7 selects the blinking mode; normal operation with frequency set by bf1, bf0 or blinking by alteration of display ram banks. alteration blinking does not apply in 1:3 or 1:4 multiplex drive modes. table 9. mode set option 1 lcd drive mode bits drive mode backplane m1 m0 static 1 bp 0 1 1:2 mux (2bp) 1 0 1:3 mux (3bp) 1 1 1:4 mux (4bp) 0 0 table 10. mode set option 2 lcd bias bit b 1 ? 3 bias 0 1 ? 2 bias 1 table 11. mode set option 3 display status bit e disabled (blank) 0 enabled 1
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 24 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates [1] normal blinking is assumed when the multiplex rates 1:3 or 1:4 are selected. 7.10 display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the PCF8534 and co-ordinates their effects. the controller is also responsible for loading display data into the display ram as required by the filling order. 7.11 cascaded operation in large display configurations, up to 16 PCF8534?s can be distinguished on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded PCF8534?s are synchronized they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of table 12. load data pointer option 1 description bits 7 bit ordinary value of 0 to 59 p6 p5 p4 p3 p2 p1 p0 table 13. device selected option 1 description bits 3 bit binary value of 0 to 7 a2 a1 a0 table 14. blank select option 1 (input) static 1:2 mux bit i ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 table 15. blank select option 2 (output) static 1:2 mux bit o ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 table 16. blink option 1 blink frequency bits bf1 bf0 off 0 0 2 hz 0 1 1 hz 1 0 1.5 hz 1 1 table 17. blink option 2 blink mode bit a normal blinking 0 [1] alteration blinking 1
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 25 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates only one device need to be through-plated to the backplane electrodes of the display. the other PCF8534?s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see figure 17 ). the sync line is provided to maintain the correct synchronization between all cascaded PCF8534?s. this synchronization is guaranteed after the power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF8534?s with different sa0 levels are cascaded). sync is organized as an input / output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. a PCF8534 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the first PCF8534 to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the PCF8534 are shown in figure 18 . the contact resistance between the sync pads of cascaded devices must be controlled. if the resistance is too high then the device will not be able to synchronize properly. ta b l e 1 8 shows the limiting values for contact resistance. table 18. sync contact resistance number of devices maximum contact resistance 2 6000 3 to 5 2200 6 to 10 1200 11 to 16 700
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 26 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates fig 17. cascaded PCF8534 configuration handbook, full pagewidth host micro- processor/ micro- controller sda scl clk osc sync 60 segment drives 4 backplanes 60 segment drives lcd panel PCF8534 a0 a1 a2 sa0 v ss v ss v ss v dd v dd v lcd v lcd v dd v lcd mgl754v02 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 PCF8534 bp0 to bp3 r t r 2c b
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 27 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates fig 18. synchronization of the cascade for various PCF8534 drive modes t= frame f frame 1 bp0 sync bp1 ( 1/2 bias) sync bp2 (a) static drive mode. (b) 1 : 2 multiplex drive mode. (c) 1 : 3 multiplex drive mode. (d) 1 : 4 multiplex drive mode. bp3 sync sync bp1 ( 1/3 bias) mgl75 5
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 28 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 8. limiting values 8.1 esd values ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 2000 v cdm per jesd22-c101. ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma. 9. static characteristics table 19. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v lcd lcd supply voltage v ss ? 0.5 +7.5 v i lcd lcd supply current ? 50 +50 ma i ss negative supply current ? 50 +50 ma v i(n) input voltage on pads sda, scl, clk, sync , sa0, osc and a0 to a2 v ss ? 0.5 v dd + 0.5 v v o(n) output voltage on pads s= to s59 and bp0 to bp3 v ss ? 0.5 v lcd + 0.5 v i i dc input current ? 10 +10 ma i o dc output current ? 10 +10 ma p tot total power dissipation - 400 mw p / out power dissipation per output - 100 mw t stg storage temperature ? 65 +150 c table 20. static characteristics v dd = 1.8 to 5.5 v; v ss = 0 v; v lcd = 2.5 to 6.5 v; t amb = ? 40 to +85c; unless otherwise specified symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 a i dd supply current f clk = 1536 hz [1] -820 a i lcd lcd supply current f clk = 1536 hz [1] -2460 a logic v il low-level input voltage v ss - 0.3 v dd v v ih high-level input voltage 0.7 v dd -v dd v i ol1 low-level output current on pads clk and sync v ol = 0.4 v; v dd = 5 v 1 - - ma
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 29 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates [1] lcd outputs are open circuit; inputs at v ss or v dd ; external clock with 50% duty factor; i 2 c-bus inactive. [2] not tested, design spec only. [3] outputs measured individually and sequentially. 10. dynamic characteristics i oh1 high-level output current pad clk v oh = 4.6 v; v dd = 5 v ? 1- - ma i ol2 low-level output current pad sda v ol = 0.4 v; v dd = 5 v 3 - - ma i l1 leakage current pads sa0, a0 to a2, clk, sda and scl v 1 = v dd or v ss ? 1- +1 a i l2 leakage current pad osc v 1 = v dd ? 1- +1 a c 1 input capacitance [2] --7pf v por power on reset voltage level 1.01.31.6v lcd outputs v bp dc voltage component on pads bp0 to bp3 c bp = 35 nf ? 100 - +100 mv v s dc voltage component on pads s0 to s59 c s = 5 nf ? 100 - +100 mv r bp output resistance at pads bp0 to bp3 v lcd = 5 v [3] -1.510k r s output resistance at pads s0 to s59 v lcd = 5 v [3] -6.013.5k table 20. static characteristics v dd = 1.8 to 5.5 v; v ss = 0 v; v lcd = 2.5 to 6.5 v; t amb = ? 40 to +85c; unless otherwise specified symbol parameter conditions min typ max unit table 21. dynamic characteristics v dd = 1.8 to 5.5 v; v ss = 0 v; v lcd = 2.5 to 6.5 v; t amb = ? 40 to +85c; unless otherwise specified symbol parameter conditions min typ max unit f clk(int) oscillator frequency on pad clk (internal clock) v dd = 5 v [1] 960 1536 3046 hz f clk(ext) oscillator frequency on pad clk (external clock) v dd = 5 v 797 1536 3046 hz t clkh input clk high time 130 - - s t clkl input clk low time 130 - - s t r clk rise time ---ns t f clk fall time ---ns t d(p)sync sync propagation delay time - 30 - ns t syncl sync low time 1 - - s t d(plcd) driver delays with test loads v lcd = 5 v --30 s timing characteristic: i 2 c bus [2] f scl scl clock frequency - - 400 khz t buf bus free time between a stop and a start 1.3 - - s
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 30 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates [1] typical output duty cycle of 50%. [2] all timing values are valid within the operating suppl y voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd. t hd;sta start condition hold time 0.6 - - s t su;sta set-up time for a repeated start condition 0.6 - - s t low scl low time 1.3 - - s t high scl high time 0.6 - - s t r scl and sda rise time - - 0.3 s t f scl and sda fall time - 0.3 s c b capacitive bus line load - - 400 pf t su;dat data set-up time 100 ns t hd;dat data hold time 0 - - ns t su;sto set up time for stop condition 0.6 - - s t sw tolerable spike width on bus - - 50 ns table 21. dynamic characteristics v dd = 1.8 to 5.5 v; v ss = 0 v; v lcd = 2.5 to 6.5 v; t amb = ? 40 to +85c; unless otherwise specified symbol parameter conditions min typ max unit fig 19. test loads gew idth mgs120v02 3.3 k 1.5 k 0.5v dd v dd v ss sda, scl clk 1 nf bp0 to bp3, and s0 to s59 (2%) (2%) 6.8 v dd sync (2%)
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 31 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates fig 20. driver timing waveforms mgl761v0 3 0.7v dd 0.3v dd 0.7v dd 0.3v dd 1/ f clk t d(p)(sync) t d(p)(sync) t clkh t clkl sync clk 0.5 v 0.5 v t plcd bp0 to bp3, a nd s0 to s59 t syncl (v dd = 5 v) t r t f fig 21. i 2 c-bus timing waveforms s da mga728 s da s cl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 32 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 11. package outline fig 22. package outline lqfp80 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale l qfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315 -1
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 33 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 12. handling information fig 23. device protection diagram handbook, full pagewidth sa0 v dd v dd v ss v ss v lcd v ss sda mgl760v02 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1 a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s59 v lcd v ss
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 34 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 13. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, including the board finish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 35 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 24 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 2 and 23 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 24 . table 22. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 23. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 36 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 24. temperature profiles for large and small components 001aac84 4 t emperature tim e minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 37 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 14. revision history table 24. revision history document id release date data sheet status change notice supersedes PCF8534_00.04 tbd preliminary PCF8534_00.03 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? table 21 : clock oscillator frequency (added external) PCF8534_00.03 20060829 objective PCF8534_00.02 modifications: ? table 1 :added column for ?topside mark? ? section 8.1 : added esd values. PCF8534_00.02 20060725 objective PCF8534_00.01 modifications: ? transfer to tdm format PCF8534_00.01 20060628 objective first release
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 38 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates 15. legal information 15.1 data sheet status [1] please consult the most recently issued docum ent before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp se miconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for additional information, please visit: http://www.nxp.com for sales office addresses, send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objective specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
PCF8534_0 ? nxp b.v. 2007. all rights reserved. preliminary datasheet rev. 00.05 ? 20 february 2007 39 of 40 nxp semiconductors PCF8534 universal lcd driver for low multiplex rates notes
nxp semiconductors PCF8534 universal lcd driver for low multiplex rates ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 20 february 2007 document identifier: PCF8534_0 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 7 6.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 7 6.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 9 6.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 6.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 10 6.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 12 6.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13 6.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 6.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 6.10 display ram. . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 16 6.13 output bank selector . . . . . . . . . . . . . . . . . . . 16 6.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 17 6.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 application design-in information . . . . . . . . . 19 7.1 characteristics of the i 2 c bus . . . . . . . . . . . . . 19 7.2 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 start and stop conditions . . . . . . . . . . . . . 19 7.4 system configuration . . . . . . . . . . . . . . . . . . . 19 7.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 PCF8534 i2c-bus controller . . . . . . . . . . . . . . 20 7.7 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.8 i2c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.10 display controller . . . . . . . . . . . . . . . . . . . . . . 24 7.11 cascaded operation . . . . . . . . . . . . . . . . . . . . 24 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 esd values . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 static characteristics. . . . . . . . . . . . . . . . . . . . 28 10 dynamic characteristics . . . . . . . . . . . . . . . . . 29 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 12 handling information . . . . . . . . . . . . . . . . . . . 33 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 34 13.2 wave and reflow soldering. . . . . . . . . . . . . . . 34 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 34 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 35 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 37 15 legal information . . . . . . . . . . . . . . . . . . . . . . 38 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 38 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 16 contact information . . . . . . . . . . . . . . . . . . . . 38 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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